Data throughputs are increasing in chip-to-chip interconnects in applications ranging from backplanes in server systems to SOCs (systems on chip) interfaced to memories in mobile devices. This trend has been pushed forward by the increasing capacity of digital computation resulting from improvements in semiconductor technology.
Although on-chip speeds may scale upward for particular technologies, the corresponding electrical interface speeds may be restricted by issues that are unrelated to the semiconductor technology.
For example, I/O drivers are a significant component in interface design, and may present a significant bottleneck in improving overall performance in terms of speed and power. Among the issues that need to be addressed are the limitations presented by circuits that either include a termination resistance, thereby creating a significant current load, or do not include a termination resistance, and thereby create a limitation in speed for the I/O interface.